Agilent Technologies has announced a strategic partnership with Aster Technologies to enable integration of Aster's TestWay Coverage Analyst with Agilent's printed-circuit-board assembly-test ...

While the analog and mixed-signal components are the leading source of test escapes that result in field failures, the lack of tools to analyze the test coverage during design has made it difficult ...

The complexity of system-on-chip (SoC) designs continues to grow, so the corresponding design-for-test (DFT) logic required for manufacturing has become more advanced. Design teams are challenged by ...

February 5, 2013. ASTER Technologies, a supplier of board-level testability and test-coverage analysis products, has developed a new release of TestWay in support of “Design for Excellence” (DfX) ...

Back in the day, we'd write some code, compile, execute, see what happened and repeat. That was testing. (Sometimes that's still what testing looks like, for better or worse.) Today, we can do a lot ...

Scan is a structured test approach in which the overall function of an integrated circuit (IC) is broken into smaller structures and tested individually. Every state element (D flip-flop or latch) is ...

While I was reviewing a whitepaper titled Fuzzing Challenges: Metrics and Coverage, I thought the topic actually would deserve a wider analysis from the perspective of penetration testing. All the ...

Richardson, Texas—A product called DFT Analyzer from ASSET InterTech, Inc., a maker of IEEE-1149.1/JTAG boundary-scan test and ISP (in-system programming) tools, promises to reduce manufacturing and ...